This invention relates to the fabrication of integrated circuits and, more particularly, to a technique for high-resolution patterning of silicide-on-polysilicon structures for metal-oxide-semiconductor (MOS) devices.
It is known to utilize a refractory metal silicide on polysilicon to achieve a high-conductivity gate-level metallization for MOS devices. Specific examples of such silicide-on-polysilicon composite structures suitable for MOS devices are described in a copending commonly assigned application of H. J. Levinstein, S. P. Murarka and A. K. Sinha, Ser. No. 974,378, filed Dec. 29, 1978, now U.S. Pat. No. 4,276,557 issued June 30, 1981. Additional details concerning the use of silicide-on-polysilicon composites in such devices are contained in an article by S. P. Murarka, D. B. Fraser, A. K. Sinha and H. J. Levinstein entitled, "Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects," IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 4, August 1980, pp. 474-482.
The effective utilization of silicide-on-polysilicon composites in very-large scale-integrated (VLSI) MOS devices to form, for example, high-resolution gate electrodes requires that fabrication techniques be available for patterning silicide and polysilicon layers anisotropically with minimal linewidth loss. Accordingly, efforts have been directed at trying to devise high-resolution etching processes for patterning such layers. For some silicides, these efforts to devise an effective etching process adequate for defining high-resolution features in VLSI devices have not been completely successful. Moreover, the efforts to incorporate and pattern silicides in such devices have been complicated by the apparent necessity of having to develop a different etching procedure for each different silicide-on-polysilicon combination.